1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing a semiconductor device, and more specifically to an SRAM (static random access memory).
2. Description of Related Art
A static memory cell is made up of two high-resistance load elements and four n-channel MOS transistors. FIG. 11 shows an equivalent circuit of a static memory cell.
Referring to FIG. 11, the drain of each of the pair of MOS driver transistors T1 and T2 is connected to the gate of other MOS driver transistor, and to each drain thereof is connected the load resistances R1 and R2, respectively, the sources of the MOS transistors T1 and T2 being fixed to the ground potential Vss.
The other ends of the resistances R1 and R2 are supplied with the power supply voltage Vcc, so that the flip-flop circuit formed by the MOS transistors T1 and T2 and the resistances R1 and R2 is supplied with a minute current. The transfer MOS transistors T3 and T4 are connected to the storage nodes N1 and N2 of this flip-flop circuit.
The above-noted four transistors and two resistances form a 1-bit cell. In this drawing FIG. 11, the reference numeral 1a denotes a word line, while 2a and 2b are data lines.
In a static memory of the past, because one end of the load resistances of the memory cell was a power supply line that was doped with a high concentration of an impurity, and the other end was connected to the MOS driver transistor, in subsequent thermal budget, because of diffusion of the impurity from the high-concentration region to the low-concentration region of the load resistance, it was necessary to have sufficient length in the resistance in order to maintain the resistance value.
However, with an increase in the degree of integration in semiconductor devices, it is becoming difficult to establish sufficient resistance length.
Because of the above-noted situation, in the Japanese Unexamined Patent Publication (KOKAI) No. 63-80566, there is proposed a configuration for the purpose of achieving a high degree of integration, while avoiding the problem of having the load resistance length govern the memory cell length, in which, in a resistive-load type of static semiconductor memory, the load resistance is made of polycrystal silicon having a multilayer structure separated by an insulation layer, each resistance layer being successively mutually connected via a connection hole which is formed in the insulation layers therebetween to the next resistance layer.
FIG. 12 will be used to describe the method of manufacturing the prior art example. FIG. 12 shows a vertical cross-sectional view of a static semiconductor memory of the past.
Referring to FIG. 12, after forming the transfer MOS transistor gate electrode 4 and driver MOS transistor gate electrode 5 on a semiconductor substrate 1, via an intervening field oxide layer 2 and gate oxide layer 3, a diffusion layer 8 is formed by ion implantation of a high concentration of an impurity.
Next, after forming an insulating layer 9, a contact hole10 is formed in a prescribed region. After forming polycrystalline silicon, photolithography and etching are used to perform patterning of a high-resistance load element 11.
Next, an insulation layer 14 is formed, and a contact hole 19 is formed in a prescribed region.
Additionally, polysilicon is formed, and photolithography and etching are used to perform patterning of a high-resistance load element 21, and then photoresist is used to mask an end of the high-resistance load element 21 and a high-concentration impurity is formed by ion implantation, this serving as the power supply line 20.
In the above-noted prior art, there is the problem that the manufacturing process is complex. The reason for this is that the load resistances are formed by connecting two layers of high-resistance polysilicon.
An additional problem is that, while it is possible to maintain the resistance length by reduction of the cell surface area, there is no means provided to increase of the node capacitance, making it impossible to establish the node capacitance.
On the other hand, the Japanese Unexamined Patent Publication (KOKAI) No.5-90540 discloses a semiconductor memory device in that a capacity layer is provided at a common contacting point so as to prevent soft ware error from occurring when .alpha. ray is radiated thereto but it fails to show or suggest to expand the length of the high-resistance load element layer.
In view of the above-described drawbacks in the prior art, an object of the present invention is to provide a semiconductor device which enables attainment of a sufficient load resistance length and also enables an increase in the node capacitance, and which provides improved operating characteristics, and also to provide a method of manufacturing the above-noted semiconductor device.